The present invention generally relates to metal oxide semiconductor (MOS) transistors and methods of producing such MOS transistors, and semiconductor devices having a high voltage MOS transistor and methods of producing such semiconductor devices. More particularly, the present invention relates to a high voltage MOS transistor which is suited for use in a boost part of a dynamic random access memory (DRAM), for example, a method of producing such a high voltage MOS transistor, a semiconductor device having such a high voltage MOS transistor, and a method of producing such a semiconductor device.
In DRAMs, the voltage applied to a word line is generally boosted to a voltage greater than or equal to the power source voltage in order to apply a sufficiently high voltage to a capacitor of a memory cell and positively write data. FIG. 1 shows an example of a bootstrap word line driver circuit for applying the boosted voltage to the word line. As shown, first and second n-type MOS transistors 551 and 552 are connected in series, and a drain d3 of a third n-type MOS transistor 553 is connected to a gate g1 of the transistor 551 at a node A.
A boost voltage Vo from a voltage boost circuit (not shown) is applied to a drain d1 of the transistor 551 via a terminal 555. A power source voltage Vcc from a power source (not shown) is applied to a gate g3 of the transistor 553 via a terminal 556. An output signal of a decoder (not shown) is applied to a source s3 of the transistor 553 via a terminal 557. The source s3 and the terminal 557 are connected at a node B. A gate g2 of the transistor 552 is coupled to a reset signal line RL via a terminal 558. A source s1 of the transistor 551 and a drain d2 of the transistor 552 are connected at a node D, and the node D is coupled to a word line WL via a terminal 559. A source s2 of the transistor 552 is grounded.
When the transistor 553 is selected by the output signal of the decoder and is turned ON, the potential at the source s3 (node B) becomes Vcc. The potential at the drain d3 (node A) becomes Vcc-Vth, where Vth denotes a threshold voltage of the transistor 553. Accordingly, the transistor 551 turns ON, the transistor 553 turns OFF and the drain d3 assumes a floating state. Since the potential at the node A is Vr which is raised greater than or equal to the boost voltage Vo due to the gate capacitance coupling of the transistor 551, the boost voltage Vo at the node D is applied to the word line WL without a voltage drop. For example, Vcc=5 V, Vo=7.5 V, and Vr=14 V.
Because the power source voltage Vcc is boosted to Vr and applied to the drain d3 of the transistor 553, a diffusion layer which forms the drain d3 must have a sufficiently high withstand voltage. If the diffusion layer forming the drain d3 does not have a sufficiently high withstand voltage, the potential at the node A gradually falls and it becomes impossible t maintain the voltage applied to the word line WL at Vo.
As a method of preventing the voltage drop at the node A, it is conceivable to make a gate oxide layer of the transistor 553 thick. However, this method would go against the recent trend which is to make the gate oxide layer thin in order to reduce the size of the semiconductor device.
FIG. 2 shows an example of a conventional high voltage MOS transistor having a lightly doped drain (LDD) structure. The drain d3 of the transistor 553 is formed by a wide n-type layer 553d which has a relatively low impurity concentration, and the high withstand voltage is realized by increasing a depletion layer which is formed at a junction interface between the n-type layer 553d and a p-type semiconductor substrate 600. In addition, because a drain electrode 601 is normally made of aluminum (Al), the drain d3 is made of an n.sup.+ -type layer 553e having a relatively high concentration at a portion where the drain d3 connects to the drain electrode 601 so as to prevent the contact resistance from becoming high. In FIG. 2, the MOS transistor also includes a field oxide layer 602, a gate oxide layer 603 and a boron phosphosilicate glass (BPSG) interlayer insulator layer 604.
There roughly are two methods of producing the conventional high voltage MOS transistor. According to a first method, a contact hole for the drain electrode 601 is formed with respect to the n.sup.+ -type layer 553e which is formed in advance. On the other hand, according to a second method, an ion implantation is made via a contact hole for the drain electrode 601 so as to form the n.sup.+ -type layer 553e in a self-aligned manner.
The first method described above will now be described with reference to FIG. 3. In FIG. 3, L.sub.1 denotes a distance between the gate g3 and the n.sup.+ -type layer 553e, L.sub.2 denotes a distance by which the BPSG interlayer insulator layer 604 and the n.sup.+ -type layer 553e overlap, and L.sub.3 denotes a distance corresponding to a width of the contact hole for the drain electrode 601. The withstand voltage of the drain d3 is determined by the distance L.sub.1. However, the contact resistance becomes too large if the n-type layer 553d makes direct contact with the A.sub.1 drain electrode 601, and the n.sup.+ -type layer 553e must be provided to make contact with the drain electrode 601. For this reason, there is a limit to reducing the distance L.sub.3 for making the contact. In addition, the drain electrode 601 may make direct contact with the n-type layer 553d if the contact hole is not formed with the margin corresponding to the distance L.sub.2 2, and there is a limit to reducing the distance L.sub.2. Accordingly, the element spreads laterally by the distance L.sub.1 +L.sub.2 +L.sub.3 in order to ensure the withstand voltage of the drain d3 which is determined by the distance L.sub.1. In other words, there is a limit to reducing the area occupied by the high voltage MOS transistor.
Next, a description will be given of the second method described above, by referring to FIGS. 4A through 4C. FIG. 4A shows a state where the contact hole is formed in the BPSG interlayer insulator layer 604 and the gate oxide layer 603. FIG. 4B shows a process of forming a resist layer 605 and thereafter carrying out an ion implantation to form the n.sup.+ -type layer 553e and an n.sup.+ -type layer 553s which forms the source s3. When carrying out the ion implantation, the impurity ions are also injected at portions indicated by "x" marks due to the positioning margin of the resist layer 605. For this reason, when a process using an HF system etchant is carried out before a process of forming an A1 layer which forms the drain electrode 601, stepped portions 610 are formed as shown in FIG. 4C because the portions injected with the impurity ions have a faster etching rate compared to other portions. When the stepped portions 610 are formed, an interconnection layer and the like which are formed thereafter may easily be damaged, and an open circuit may occur in the case of the interconnection layer. This second method forms the n.sup.+ -type layer 553e in the self-aligned manner, and thus the distance L.sub.2 can be reduced when compared to the first method. However, there is a limit to reducing the area occupied by the high voltage MOS transistor because the distance L.sub.1 +L.sub.2 +L.sub.3 is still required. Further, the number of processes required in the second method is larger when compared to that required in the first method.